Datasheet

7–64
Results
Laboratory data were taken using the demonstration backplane and compared to HSPICE simulation results to validate the
performance of the GTL16622A on the backplane. Figure 7 is the reference to give the position of driver and receiver cards
in the backplane. Results for TI’s newest addition, the GTL16612A, demonstrate the throughput capability in a very
high-performance backplane.
Laboratory
Figure 9 shows the laboratory results for the GTL16622A, with all 36 bits switching on the fully loaded backplane board with
the driver card in slot 1. The worst-case signal was observed in the receiver card closest to the driver card (slot 2), while the
best-case signal was seen in the receiver card farthest from the driver (slot 16). The throughput obtained at 50 MHz is 1.8 Gbit/s.
15
Voltage – V
Time – ns
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
20 25 30 35 40 45 50 55 60 65 15
Time – ns
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
20 25 30 35 40 45 50 55 60 65
Driver in Slot 1
Receiver in Slot 2
Upper and Lower
Threshold Levels
Driver in Slot 1
Receiver in Slot 16
Upper and Lower
Threshold Levels
Voltage – V
Figure 9. GTL16622A Signal Integrity (Laboratory Results)
Simulation
Figure 10 shows the HSPICE simulation results for the GTL16622A, which correlate closely with results observed in the
laboratory with the demonstration hardware. The simulation results are observed after modeling the backplane using HSPICE
for single-bit switching.
Voltage – V
Time – ns
0.4
0.6
0.8
1.0
1.4
1.6
1.8
20 30 40 50 60
1.2
2.0
Driver in Slot 1
Receiver in Slot 2
Time – ns
0.4
0.6
0.8
1.0
1.2
1.4
1.6
20 30 40 50 60
1.8
Driver in Slot 1
Receiver in Slot 16
Voltage – V
Figure 10. GTL16622A Signal Integrity (HSPICE Simulation Results)