Datasheet

7–60
01020304050607080
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Voltage – V
Time – ns
Figure 4. GTL16622A H-SPICE Simulation (Lumped Load, 33 MHz)
10
Voltage – V
Time – ns
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
020304050607080
Figure 5. GTL16622A H-SPICE Simulation of a Backplane (Distributed Load, 33 MHz)
The added capacitance and inductance in the distributed load cause reflections that result in problems that include reduced noise
margins.
3
In this case, the signal on the bus must settle before being sampled, hence, the bus settling time is required before
valid data can obtained. Table 1 shows the comparison for the noise margins obtained for GTL and GTL+. GTL+ provides a
wider noise margin than GTL, an important factor for designing signal-integrity-critical applications. In high-performance
backplane designs, termination voltage, bus impedance, termination resistance, stub lengths, and driver and receiver
characteristics must be controlled carefully to achieve good signal integrity, so that valid data can be presumed at the incident
wave of the signal.