Datasheet

758
V
OH
V
IH
V
REF
V
IL
V
OL
GND
GTL
1.2 V
0.85 V
0.8 V
0.75 V
0.4 V
0
V
OH
V
REF
GND
GTL+
1.5 V
1.0 V
0
V
IH
1.2 V
V
IL
V
OL
0.8 V
0.6 V
Figure 1. GTL/GTL+ Switching Levels
GTL+ achieves high performance with the help of the low signal voltage swing.
1
The typical swing for GTL+ is from 0.6-V low
(V
OL
) to 1.5-V high (V
OH
) maximum. TI uses tighter threshold regions, V
IH
at 1.05 V, V
IL
at 0.95 V, and V
OL
at 0.55 V, to
provide better signal integrity in its stand-alone devices. This report demonstrates the performance of the newest TI GTL+
devices operating at clock rates of 100 MHz, providing bit rates of up to 10 Gbit/s in a 100-bit-wide backplane bus.
The TI GTL family offers edge control, which reduces signal noise and electromagnetic interference (EMI). The basic GTL
output structure is an open-drain transistor, whereas the input is a differential receiver.
2
Also, the GTL I/Os have been designed
to minimize their capacitance, an extremely important factor for distributed-load high-performance backplanes.
Backplane Design Considerations
This section covers the electrical elements of the backplane. The backplane bus connects the different modules in a backplane.
The wires and traces on the bus and the traces on the modules are electrical elements that are a connection point for the various
electrical modules. It is necessary to understand these electrical elements (such as impedance, capacitance, inductance,
termination, connectors, stub lengths, vias, and driver and receiver characteristics) to design a successful backplane.
All of the above parameters contribute to the performance of the backplane. Backplanes can be categorized as low performance,
medium performance, or high performance. A low-performance backplane can be modeled as a lumped load; medium- and
high-performance backplanes must be viewed as a distributed load, by applying transmission-line theory.
With a low-performance backplane, the backplane driver sees the load as a lumped capacitance. The capacitive load in many
cases is still distributed; however, it is modeled as a lumped load. This lumped model is used where the rise time of the signal
is small compared to the transition time along the backplane. Here, only the final state matters, and bus performance is not the
highest concern. The lumped capacitance is charged or discharged by the driver (see Figure 2) and is controlled by the RC time
constant. The low-to-high signal transition is indicated by 1 e
t/RC
and the high-to-low signal transition is of the form e
t/RC
.
This lumped capacitance is referred to in the industry as a lumped load.
V
T
R
T
V
(t)
I
T
V
T
R
T
V
(t)
I
1
I
3
C
lumped
C
lumped
R
d
I
2
R
T
= Termination Resistance R
d
= Driver Resistance
High-to-Low TransitionLow-to-High Transition
V
(t)
+ V
T
ƪ
R
d
R
d
) R
T
)
ǒ
R
T
R
d
) R
T
Ǔ
e
*tńRC
ƫ
,whereR+
R
T
R
d
R
d
) R
T
V
(
t
)
+ V
T
ǒ
1 * e
*tńRC
Ǔ
Figure 2. Lumped-Load Effects