Datasheet

SCBA015A
7–31
Fast GTLP Backplanes With the GTLPH1655
TI-OPC Circuitry
TI-OPC circuitry is a new feature of the GTLP backplane family.
This circuit improves signal integrity by using a control circuit that compares the output voltage
at the GTLP port with the reference voltage. The principle is shown in Figure 21.
TI-OPC
V
TT
V
REF
R
TT
Figure 21. TI-OPC Circuitry Replacement of GTLP
If the output voltage exceeds about one diode forward voltage referred to the reference voltage,
the TI-OPC circuitry limits currents below about 14 mA to the voltage to V
REF
+ V
diode
. If this
output current is exceeded, the output resistance increases again rapidly (compare to
Figure 19).
Edge-Rate Control (ERC)
In the GTLP output stage, a circuit is included that allows two different values of edge rate to be
set. With the use of the ERC input pin, different rise and fall times can be set, allowing the
optimum configuration under various loading conditions of the backplane. If the
SN74GTLPH1655 ERC is connected to the supply voltage (V
CC
), the GTLP outputs are
switched with longer rise and fall times than when it is connected to GND. Some GTLP devices
have the ERC
feature, which is the opposite of ERC. If ERC is connected to GND, the GTLP
outputs are switched with a longer rise and fall time.
In two series of measurements, the voltage at the control input ERC was varied to determine the
influence of the ERC circuit on the behavior of the signal.
As shown in Figure 22, the measurements on the SN74GTLPH1655 were made with a single
device under no-load conditions, using GTLP voltage levels. During the measurement, only the
25-Ω pullup resistor was at the GTLP output. There were LVTTL signals from a signal generator
at the A port of the device, each having different rise and fall times: t
r
, t
f
= 2 ns and t
r
, t
f
= 10 ns.