Datasheet
SCBA015A
7–19
Fast GTLP Backplanes With the GTLPH1655
GTL Bus
As shown in Figure 10, the basic circuit layout of the GTL bus is very similar to that of BTL. In
this case, there also is a system with open-drain drivers and correct bus termination. The
voltage levels of the logic states are 0.4 V in the low-logic state, and 1.2 V in the high-logic state.
The signal amplitude is reduced to 0.8 V, whereby the threshold voltage lies exactly between the
low and high levels, also at 0.8 V.
Z
O
R
TT
= Z
O
GTL Bus
V
REF
= 0.8 V
Driver
Receiver
+1.2 V
Figure 10. Circuit Concept of GTL Bus
In contrast to the BTL circuits, the drive capability of the output transistor is 40 mA. Therefore,
the lower limit of the termination resistance (also of the line impedance) is 20 Ω (0.8 V/40 mA).
For a driver connected to the middle of a bus line, the limit for the impedance of the line is 40 Ω.
To attain impedance of the bus lines of 40 Ω, the capacitive component of the line must not be
too high. Therefore, GTL is not the first choice when driving extensive backplane wiring with
many modules.
Since the GTL bus was conceived for smaller buses on a circuit board, for example a memory
bus between CPU and memory modules, the specification does not include the precharge
function. The reason is that, when the bus is on a circuit board, there is no question of
withdrawal and reinsertion during operation.