Datasheet
SCBA015A
7–17
Fast GTLP Backplanes With the GTLPH1655
New Bus Systems Are Needed
The cause of most problems with bus lines is the distributed capacitive loading on the line by the
modules connected to it. The impact on TTL and CMOS buses is:
• Very low signal speed on the line (about 25 ns/m, instead of 5 ns/m)
• The impedance of the line is reduced from about 80 Ω to about 25 Ω.
• As a result of the low impedance, adequate incident-wave amplitude is possible only with
extremely low-resistance drivers.
• Correct termination is not possible because, otherwise, excessively high currents would flow
through the terminating resistors.
It is not possible to solve these problems adequately with the circuit techniques commonly used
with TTL- and CMOS-compatible circuits. With the commonly used techniques, it always would
be necessary to accept a compromise in the circuit layout.
To develop a new bus system meeting the requirements imposed by the situation mentioned
above requires the following:
• The capacitance of a module must be reduced, and also the capacitance of the I/O pins of
the bus-driver circuit.
– Because of the reduced capacitive component of the bus line, the impedance is reduced
only to about 30 Ω.
– The smaller capacitive component also results in less degradation of the signal speed (to
about 20 ns/m).
• The drivers must be of low resistance to switch the bus with the incident wave.
• The signal amplitude must be reduced to allow correct termination of the line impedance. For
example, with a signal amplitude of 1 V, a termination resistor of 30 Ω is adequate because
the current flowing is only 33 mA per signal line.
The two bus systems that meet these basic physical requirements are BTL and GTL.