Datasheet

SCBA015A
7–13
Fast GTLP Backplanes With the GTLPH1655
Effects on Bus Lines
Beginning of the Line: The Incident Wave
A fundamental characteristic of bus drivers is their output resistance. Together with the line
impedance, this forms a voltage divider (Equation 3) and, thus, is responsible for the amplitude
of the incident voltage wave.
If the driver can generate an incident voltage edge that has an amplitude above (below) the
defined voltage threshold for the high logic state (low logic state), the logic level of all inputs that
are connected on the bus will be changed over with the incident wave. For TTL-compatible bus
systems, the rising edge of the incident voltage wave must exceed 2 V, and the falling edge
must fall below 0.8 V. To calculate the maximum signal delay on the bus for an
incident-wave-switching system, only the simple line propagation delay must be added to the
delay time of the driver circuit (see Table 3).
Table 3. Signal Delay Using Figure 6 as an Example
SWITCHING WITH THE
INCIDENT WAVE
SWITCHING WITH THE
REFLECTED WAVE
A⇒B
t
pd Driver
+ t
pd Receiver
= 5 ns + 5 ns
= 10 ns
t
pd Driver
+ t
pd Line
+ t
pd Line
+ t
pd Receiver
= 5 ns + 10 ns + 10 ns + 5 ns
= 30 ns
A⇒C
t
pd Driver
+ t
pd Line
+ t
pd Receiver
= 5 ns + 10 ns + 5 ns
= 20 ns
t
pd Driver
+ t
pd Line
+ t
pd Receiver
= 5 ns + 10 ns + 5 ns
= 20 ns
Worst case 20 ns 30 ns
L
O
≈ 6 nH/cm
Z
O
= 25 Ω
t
pd
= 5 ns
d = 2 cm
C
O
≈ 10 pF/cm
τ = 25 ns/m
t
pd
= 5 ns
I = 40 cm
AB C
Figure 6. Example of a Bus Line
However, if the amplitude of the incident wave is insufficient, it is necessary to wait until the
reflected wave returns from the end of the line to the beginning. Only then is a valid logic level
reached on the entire bus line. In the example of Figure 6, according to Table 3, the signal delay
time of 30 ns maximum results. Thus, when compared with switching with the incident wave, the
signal delay time of the system is increased by 10 ns, or 50%.