Datasheet
SCBA015A
7–7
Fast GTLP Backplanes With the GTLPH1655
Physical Principles
In data sheets, the delay times of driver circuits are commonly given with a load circuit of 50 pF
and 500 Ω at the outputs. However, this load circuit does not correspond well to the actual
effective loads in current application. Rather, it is intended to match the conditions existing with
IC testers. In particular, a load of this kind does not correspond to reality with bus systems. If the
connecting line between two components is compared with the relationship on a bus line,
significant differences exist.
Does a Line Behave Like a Capacitive Load?
The conditions shown in Figure 1 represent a typical connecting line between two components.
If the connecting line is 20 cm long, then there is a very small capacitive load of 12 pF. As shown
in Figure 2, modules are connected to a bus line with a 2-cm space between them, and these
contribute an additional capacitive loading of 20 pF/2 cm (= 10 pF/cm) (see Table 1). A typical
bus line on the backplane wiring of a 19-inch rack having a length of 40 cm, therefore, has a
total capacitance of 424 pF (10.6 pF/cm × 40 cm).
The development engineer needs to know the effect of the capacitive load on the signal delay of
drivers under the previously mentioned conditions (C
L
= 12 pF, or C
L
= 424 pF). The delay times
given in data sheets assume a load of 50 pF.
However, now the line cannot be considered a capacitive load, but instead must be treated from
the point of view of transmission-line theory. With the bus line described previously, a signal
delay of 10 ns (25 ns/m × 0.4 m) from one end of the line to the other is observed. If a pulse
edge is applied at the beginning of the line having a rise time of 2 ns, the signal proceeds 8 cm
(2 ns/25 ns/m) within this rise time. During this pulse edge, nothing happens over the length of
the rest of the bus line (32 cm). Therefore, during this time, the capacitance of a 32-cm line
(340 pF) has not been charged. The capacitance of this part of the line has no influence on the
waveform or the signal delay of the driver circuit.
C
in
L
O
C
O
C
O
C
O
L
O
L
O
L
O
≈ 6 nH/cm
C
O
≈ 0.6 pF/cm
Z
O
= 100 Ω
τ = 6 ns/m
Figure 1. Physical Relationships on a Connecting Line Between Two Components