Datasheet

SCBA015A
7–6
Fast GTLP Backplanes With the GTLPH1655
Introduction
Since the 1970s, bus systems have been used in every microprocessor system. In the early
systems, the delay time of the driver was in the range of 15 ns to 20 ns, and the frequency of the
system clock was about 1 MHz. The speed of the total system was determined primarily by the
delay time of the active electronics, for example, the processor, gates, and bus drivers.
With increasing clock rates, the bus began to limit the performance of the total system. To
circumvent this limitation, numerous improvements have been introduced in modern bus
systems:
Pipelining By pipelining, instructions and data are transmitted continually from the
memory to the processor.
Cache memory To avoid having the fast processor continually waiting for the slow main
memory (DRAM, EPROM), an intermediate storage of the current data is
implemented in a fast cache memory.
Block transfer The transfer of individual words of data is replaced by the transmission of
complete data blocks.
Multimaster Every device connected to the bus can initiate the transmission of data. The
cumbersome and slow route of transferring data exclusively via the CPU is,
therefore, no longer necessary.
Bus width The bus width has grown from 8 bits to 64 bits, and larger.
Clock rate The clock rate of the backplane has increased into the range of many tens of
megahertz, e.g., with a PCI bus to 33 MHz or 66 MHz. The processor itself
operates internally at far higher clock rates, e.g., at 400 MHz. The memory is
connected by a dedicated bus that operates at very high clock rates, e.g., up to
400 MHz. The memory is connected by a special bus (e.g., the
Direct
RAMBUS ), operating at 800 MHz) to the processor.
The first sections of this application report deal exclusively with general physical principles and
conditions. The engineer developing a bus system must be concerned with these to achieve
high data rates on the bus.
Circuit solutions based on TTL, BTL, and GTL logic families are compared. Particular attention is
devoted to the GTLP transceiver circuit having increased drive capability and support for live
insertion.
The SN74GTLPH1655 is presented and examined in detail.
Direct RAMBUS is a trademark of Rambus Inc.