Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VITA 2.1 SIMULATION PROPOSAL FOR THE SN74VMEH22501
introduction
This document is intended to form the basis of a statement of work for performance of simulation studies on
standard VME64x backplanes using VITA 1.5 (draft, 2eSST) protocol.
scope
The scope of this VITA 2.1 simulation effort is to:
D Determine the optimum driver characteristics (rise/fall time, rise/fall time variation, or output current) that
will support 2eSST protocol over a maximum number of slots (goal is 21 slots) with the SN74VMEH22501
model and a standard VME64x backplane. This will be performed over worst-case variations in backplane
loading, unbalanced signal loading, driving slot, transceiver drive strength, transceiver rise/fall time, and
line impedance.
D Verify support of 2eSST protocol over 21 slots with SN74VMEH22501 model and a standard VME64x
backplane. This will be performed over worst-case variations in backplane loading, unbalanced signal
loading, driving slot, transceiver drive strength, transceiver rise/fall time, and line impedance.
topology
The exact topology and transceiver loading need to be defined. The strawman proposal is that we use:
D Single-line connector models for all slots except driver and monitored receiver slots, and except for the
crosstalk simulation, which requires multiline connector models for all slots
D Multiline connector models for all driver and monitored receiver slots
D 0.841-in. backplane traces at 174-ps/in. single-line model, except for crosstalk simulation, which requires
multiline coupled transmission-line models for backplane, based on two traces routed between rows of the
DIN connector
D 1.5-in. VME board traces at 174 ps/in.
D 1.5 pF for the via on the backplane associated with the press-fit connector hole
D 0.5 pF for the via on the VME board that brings the inner-layer trace to the surface-mount receiver pad
D 0.5 pF for the via on the VME board associated with press-fit connector hole
D TI driver model with adjustable rise/fall time and adjustable drive strength
D TI diode model for the receiver clamp diode
D 8-pF lumped receiver load (total, including the capacitance of diode model). This does not represent worst
case of all legacy boards, but is representative of modern designs.
D Drive strength for weak and strong start out using TI-defined values. This must be defined before work can
start (defined in the models, action complete).
D TI to define process variation (percentage process variation from minimum to maximum) for high/low drive
strength and rise/fall time. This must be defined before work can start (defined in the models, action
complete).
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