Datasheet
SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
protocol
The basic single-cycle VMEbus data-transfer protocol is straightforward. The master puts addresses on the bus,
delays a minimum of 35 ns, then asserts address strobe (AS*). For a write operation, the master puts data on
the bus, delays a minimum of 35 ns, then asserts one or both of its data strobes (D50* and/or DS1*). All slave
cards on the bus monitor the addresses. Each slave is set up to decode a unique address. The assertion of AS*
tells the slave that the address is valid. In a write cycle, the selected slave must then read data off the bus. The
assertion of data strobe tells the slave that data is valid on the bus and can be strobed into memory. The slave
then asserts DTACK* to signal that the data has been captured.
The 2eVME protocol uses the same asynchronous protocol as the basic single-cycle protocol, but clocks data
across the bus on both the rising and falling edges of the data strobes, thus, gaining a 2× speed up for each
cycle. 2eSST, on the other hand, uses a synchronous protocol that clocks data using DS0* for writes and
DTACK* for reads. 2eSST increases the speed of the clocks to speed up the data transfers and requires the
use of a backplane that ensures monotonic signals, such as provided by the VME320 star-configuration
backplane.
applicability
Target applications for VME backplanes and ETL devices include industrial controls, military, aerospace,
transportation, telecommunications, simulation, medical, high-energy physics, office automation, and
instrumentation systems.
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