Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
driver in slot 1, with one receiver in slot 21 (minimum load) (continued)
In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into
distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and
high-to-low (HL) values in the lumped load shown in the PMI (see Figures 1 and 2).
5
5.2
5.4
5.6
5.8
6.0
6.2
6.4
HL
LH
Full B/P Load Minimum B/P Load PMI Lumped Load
Time – ns
Figure 5
Characterization-laboratory data in Figures 6 and 7 show the absolute ac peak output current with different supply
voltages as the devices change output logic state. Strong, nominal, and weak process variations are shown to
demonstrate the devices’ capability.
Figure 6
120
130
140
150
160
170
180
3 3.15 3.30 3.45 3.60
Peak I
O(LH)
– mA
V
CC
– V
Strong
Nominal
Weak
Figure 7
120
130
140
150
160
170
180
3 3.15 3.30 3.45 3.60
Peak I
O(HL)
– mA
V
CC
– V
Strong
Nominal
Weak
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