Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A JULY 2001 REVISED SEPTEMBER 2001
6–16
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics tables show the switching characteristics of the device into the lumped load
shown in the parameter measurement information (PMI) (see Figures 1 and 2). All logic devices are currently tested
into this type of load. However, the designers backplane application is probably a distributed load. For this reason,
this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3.
5 V
.42” .84”
1.5” 1.5”
1.5”1.5”
.84” .42”
Rcvr
Rcvr
Rcvr
Slot 2 Slot 3 Slot 19 Slot 20
Conn.
Conn. Conn. Conn.
1.5”
Rcvr
Slot 1
Conn.
.42”
Drvr
1.5”
Slot 21
Conn.
.42”
330
470
Z
O
5 V
330
470
Z
O
Unloaded backplane trace natural impedence (Z
O
) is 45 Ω. 45 to 60 is allowed, with 50 being ideal.
Card stub natural impedence (Z
O
) is 60 .
Rcvr
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of
the device into the backplane under full and minimum loading conditions, to help the designer better understand the
performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information.
driver in slot 11, with receiver cards in all other slots (full load)
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP
§
MAX UNIT
t
PLH
5.9 8.5
t
PHL
1A or 2A
1B or 2B
5.5 8.7
ns
t
r
Transition time, B port (10%–90%)
9 8.6 11.4 ns
t
f
Transition time, B port (90%–10%)
8.9 9 10.8 ns
§
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
All t
r
and t
f
times are taken at the first receiver.
PRODUCT PREVIEW