Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A JULY 2001 REVISED SEPTEMBER 2001
6–15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
B PORT
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
t
PLH
t
PHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
V
OL
+ 0.3 V
V
OH
0.3 V
0 V
3 V
0 V
0 V
t
w
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
A-to-B Skew
Open
6 V
GND
Open
TEST S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z
O
= 50 , t
r
2 ns, t
f
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
0 V
3 V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW