Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating conditions for UBT transceiver (unless
otherwise noted) (see Figures 1 and 2)
MIN MAX UNIT
f
clock
Clock frequency MHz
LE high
t
w
Pulse duration
CLK high or low
ns
↑
Data high
3A before CLK
↑
Data low
↓
CLK high
3A before LE
↓
CLK low
t
su
Setup time
↑
Data high
ns
3B before CLK
↑
Data low
↓
CLK high
3B before LE
↓
CLK low
↑
Data high
3A after CLK
↑
Data low
↓
CLK high
3A after LE
↓
CLK low
t
h
Hold time
↑
Data high
ns
3B after CLK
↑
Data low
↓
CLK high
3B after LE
↓
CLK low
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP MAX UNIT
t
PLH
t
PHL
1A or 2A
1B or 2B ns
t
PLH
t
PHL
1A or 2A
1Y or 2Y ns
t
PZH
t
PZL
OEAB
1B or 2B ns
t
PHZ
t
PLZ
OEAB
1B or 2B ns
t
r
Transition time, B port (10%–90%)
ns
t
f
Transition time, B port (90%–10%)
ns
t
PLH
t
PHL
1B of 2B
1Y or 2Y ns
t
PZH
t
PZL
OEBY
1Y or 2Y ns
t
PHZ
t
PLZ
OEBY
1Y or 2Y ns
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