Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
3B1
CLKAB
LE
CLKBA
3A1
To Seven Other Channels
OE
DIR
1OEAB
1OEBY
1A
1Y
2OEAB
2OEBY
2A
2Y
2B
1B
48
1
2
3
41
8
5
6
14
24
32
11
17
9
46
43
40
Pin numbers shown are for the DGG and DGV packages.
PRODUCT PREVIEW