Datasheet
SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description for 8-bit UBT transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE
is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS
OE DIR
OUTPUT
H X Z
L H 3A data to 3B bus
L L 3B data to 3A bus
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data
is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
UBT TRANSCEIVER FUNCTION TABLE
†
INPUTS
OUTPUT
OE LE CLKAB 3A
3B
MODE
H X X X Z Isolation
L L H X B
0
‡
L LLXB
0
§
Latched storage of 3A data
L H X L L
L HXHH
True transparent
L L ↑ L L
L L ↑ H H
Clocked storage of 3A data
†
3A-to-3B data flow is shown; 3B-to-3A flow is similar, but uses CLKBA.
‡
Output level before the indicated steady-state input conditions were established,
provided that CLKAB was high before LE went low
§
Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 1.
Table 1. SN74VMEH22501 UBT Transceiver Replacement Functions
FUNCTION 8 BIT
Transceiver ’245, ’623, ’645
Buffer/driver ’241, ’244, ’541
Latched transceiver ’543
Latch ’373, ’573
Registered transceiver ’646, ’652
Flip-flop ’374, ’574
SN74VMEH22501 UBT transceiver replaces all above functions
PRODUCT PREVIEW