Datasheet

SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The B port operates at ETL levels, while the 1A and 2A inputs, 1Y and 2Y outputs, 3A port, and control inputs
operate at LVTTL logic levels. All are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry prevents damaging current to backflow through the device when it is powered down. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which
prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the ETL B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, output-enable (OE
and OEBY) inputs should be tied
to V
CC
through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
terminal assignments
123456
A 1OEBY NC NC NC NC 1OEAB
B 1Y 1A GND GND V
CC
1B
C 2Y 2A V
CC
V
CC
BIAS V
CC
2B
D 3A1 2OEBY GND GND 2OEAB 3B1
E 3A2 LE V
CC
3B2
F 3A3 OE V
CC
3B3
G 3A4 CLKBA GND GND CLKAB 3B4
H 3A5 3A6 V
CC
V
CC
3B6 3B5
J 3A7 3A8 GND GND 3B8 3B7
K DIR NC NC NC NC V
CC
NC – No internal connection
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74VMEH22501DGGR
0°C to 85°C
TVSOP – DGV Tape and reel SN74VMEH22501DGVR
VFBGA – GQL Tape and reel SN74VMEH22501GQLR
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
PRODUCT PREVIEW
GQL PACKAGE
(TOP VIEW)
123456
A
B
C
D
E
F
G
H
J
K