Datasheet
SN74VMEH22501
LVTTL-TO-ETL 8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS
TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SCES357A – JULY 2001 – REVISED SEPTEMBER 2001
6–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Modes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
(EMI)
D Compliant With 2eVME and 2eSST Protocol
D Bidirectional Interface Between ETL and
LVTTL Logic Levels
D Bus Transceiver Split LVTTL Port Provides
a Feedback Path for Control and
Diagnostics Monitoring
D ETL and LVTTL Interfaces Are 5-V Tolerant
D Very Low Ground Bounce
D ETL Outputs (–48 mA/48 mA)
D LVTTL Outputs (–12 mA/12 mA)
D I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D Bus Hold on 3A-Port Data Inputs
D 26-W Equivalent Series Resistor on
3A Ports and Y Outputs
D Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
description
This 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is designed for 3.3-V
V
CC
operation with 5-V tolerant inputs. The SN74VMEH22501 provides true LVTTL-to-ETL and ETL-to-LVTTL
signal-level translation. The UBT transceiver allows transparent, latched, and flip-flop modes of data transfer,
and the separate LVTTL input and outputs on the bus transceivers provide a feedback path for control and
diagnostics monitoring. This device provides a high-speed interface between cards operating at LVTTL logic
levels and VME64x or VME320
†
backplanes operating at ETL signal levels.
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been
designed and tested into the VME64x backplane model. The ETL outputs are optimized for driving large
capacitive loads and include modified input level (V
IH
/V
IL
) for increased noise immunity and reduced input skew.
These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in
VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on
linear backplanes and possibly 1-Gbyte transfer rates on the VME320 backplane.
†
VME320 is a patented backplane construction by Arizona Digital, Inc.
PRODUCT PREVIEW
Copyright 2001, Texas Instruments Incorporated
OEC, UBT, and Widebus are trademarks of Texas Instruments.
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1OEBY
1A
1Y
GND
2A
2Y
V
CC
2OEBY
3A1
GND
LE
3A2
3A3
OE
GND
3A4
CLKBA
V
CC
3A5
3A6
GND
3A7
3A8
DIR
1OEAB
V
CC
1B
GND
BIAS V
CC
2B
V
CC
2OEAB
3B1
GND
V
CC
3B2
3B3
V
CC
GND
3B4
CLKAB
V
CC
3B5
3B6
GND
3B7
3B8
V
CC
DGG OR DGV PACKAGE
(TOP VIEW)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.