Datasheet

vi
GTL FAMILY SUMMARY
Primary features of the GTL devices:
• 3.3-V or 3.3/5-V V
CC
operation with 5-V tolerant LVTTL inputs and outputs (I/Os)
(except GTL1655), which allows the devices to act as 5-V TTL-to-GTL/GTL+, as
well as 3.3-V LVTTL-to-GTL/GTL+, translators.
• GTL1655 supports live insertion with backplane precharge circuitry.
• High point-to-point frequencies with acceptable short-backplane frequencies. The
GTL16612 transition device provides for higher distributed load (RLC) frequencies
(>60 MHz), due to its optimized edge rate.
GTL+
FREQUENCY
DEVICE FUNCTION
DRIVE
(mA)
MAX p-p
(MHz)
MAX RLC
(MHz)
Medium-Drive Devices
SN74GTL16612A 18-bit universal bus transceiver 34 85 >60
SN74GTL16616 17-bit universal bus transceiver with buffered clock 50 95 25–33
SN74GTL16622A 18-bit bus transceiver 50 200 25–33
SN74GTL16923 18-bit bus transceiver 50 200 25–33
High-Drive Devices
SN74GTL1655 16-bit universal bus transceiver 100 160 25–33
Additional features of GTL devices:
• I
off
circuitry prevents damage to the device during partial power down, a feature of
all GTL devices (see I
off
in the data sheets).
• Power-up 3-state (PU3S) forces outputs to the high-impedance state during power
up and power down, which prevents driver conflict during hot swap or hot insertion,
a feature of the GTL1655 (see I
OZPU
and I
OZPD
in the data sheets).
• BIAS V
CC
circuitry allows easy internal precharging of backplane I/O pins for true
live-insertion applications where active backplane data cannot be suspended or
disturbed during circuit-board insertion or removal, a feature of the GTL1655 (see
BIAS V
CC
in the data sheets).
• Bus hold is a feature of all GTL devices. It eliminates floating inputs by holding them
at the last valid logic state. This eliminates the need for external pullup and
pulldown resistors on unused or undriven inputs, reducing power requirements,
cost, and board-layout time. There is no bus-hold circuitry on the B port (GTL/GTL+
side) because this defeats the purpose of open-drain outputs that take on the
high-impedance state, which allows the bus to achieve a logic-high state via the
pullup resistors.
• OEC circuitry controls the rising and falling edges of the GTL16612 GTL/GTL+
outputs, and reduces line reflections and EMI, thereby improving overall signal
integrity.
• Edge-rate control (ERC) is featured on the high-drive GTL1655. Fast or slow edge
rates are achievable by holding the ERC pin at V
CC
or GND, respectively.
• GTL devices are available in the shrink small-outline package (SSOP) (56-pin
GTL16612 and GTL16616 only) and thin shrink small-outline package (TSSOP)
(56 pins or 64 pins).