Datasheet

SN74FB1653
17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE
SCBS702E AUGUST 1997 REVISED JUNE 2001
5–29
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PHZ
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
6 V
Open
500
500
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
6 V
GND
t
PHL
t
PLH
Output
Output
Control
(see Note B)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PLZ
t
PZH
t
PZL
3 V
3 V
0 V
V
OH
V
OL
0 V
V
OL
+ 0.3 V
V
OH
0.3 V
0 V
3 V
Data Input
Timing Input
3 V
0 V
3 V
0 V
3 V
0 V
t
w
Input
Output
t
PHL
t
PLH
2 V
1 V
V
OH
V
OL
Input
From Output
Under Test
LOAD CIRCUIT FOR B OUTPUTS
2.1 V
16.5
Input
C
L
= 30 pF
(see Note A)
Test
Point
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A to B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A port)
GND
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR 10 MHz, Z
O
= 50 Ω, t
r
2.5 ns,
t
f
2.5 ns; BTL inputs: PRR 10 MHz, Z
O
= 50 , t
r
1 ns, t
f
1 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V 1.5 V
1.55 V 1.55 V
1.55 V 1.55 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
t
h
t
su
Figure 1. Load Circuits and Voltage Waveforms