Datasheet

SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K – JUNE 1994 – REVISED AUGUST 2001
2–15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Members of Texas Instruments’ Widebus
Family
D UBT Transceivers Combine D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, or Clock-Enabled Modes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
D Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D Identical to ’16601 Function
D I
off
Supports Partial-Power-Down Mode
Operation
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
description
The ’GTL16612 devices are 18-bit UBT
transceivers that provide LVTTL-to-GTL/GTL+
and GTL/GTL+-to-LVTTL signal-level translation.
They combine D-type flip-flops and D-type latches
to allow for transparent, latched, clocked, and
clock-enabled modes of data transfer identical to
the ’16601 function. The devices provide an
interface between cards operating at LVTTL logic
levels and a backplane operating at GTL/GTL+
signal levels. Higher-speed operation is a direct
result of the reduced output swing (<1 V), reduced
input threshold levels, and OEC circuitry.
The user has the flexibility of using these devices at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or the preferred
higher noise margin GTL+ (V
TT
= 1.5 V and V
REF
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
REF
is the reference input voltage for the B port.
V
CC
(5 V) supplies the internal and GTL circuitry while V
CC
(3.3 V) supplies the LVTTL output buffers.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OEC, UBT, and Widebus are trademarks of Texas Instruments.
SN54GTL16612 . . . WD PACKAGE
SN74GTL16612 . . . DGG OR DL PACKAGE
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OEAB
LEAB
A1
GND
A2
A3
V
CC
(3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
(3.3 V)
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
V
CC
(5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.