Datasheet
SN74FB1653
17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE
SCBS702E – AUGUST 1997 – REVISED JUNE 2001
5–21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Compatible With IEEE Std 1194.1-1991
(BTL)
D LVTTL A Port, Backplane Transceiver Logic
(BTL) B
Port
D Open-Collector B-Port Outputs Sink
100 mA
D B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
D High-Impedance State During Power Up
and Power Down
D Selectable Clock Delay
D TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
D BIAS V
CC
Minimizes Signal Distortion
During Live Insertion/Withdrawal
PCA PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1B2
GND
1B3
1B4
GND
1B5
1B6
GND
1B7
1B8
GND
1B9
2SEL2
2CLKAB
GND
2B2
2B3
GND
2B4
2B5
GND
2B6
2B7
GND
2B8
GND
2AO6
GND
2AO7
2AO8
V
CC
2AI7
2CLKAB
2OEA
2LEAB
GND
2AO9
GND
1OEB
1OEA
1LEAB
2OEB
2OEB
2LEBA
2CLKBA
1CLKAB
2AI8
GND
1AO12AI9
2OEA
2AI6
2B9
1B1
BG V
CC
1OEB
1LEBA
1CLKBA
1OEA
1AI1
1AO2
1AI2
1AO3
1AI3
1AO4
1AI4
1AO5
1AI5
2AO5
2AI5
(5 V)
V
CC
(3.3 V)
V
CC
(5 V)
GND
1AO6
1AI6
1AO7
1AI7
GND
1AO8
1AI8
1AO9
1AI9
GND
2CLK
V
CC
(3.3 V)
2AO2
2AI2
GND
2AO3
2AI3
2AO4
2AI4
GND
V
CC
(5 V)
V
CC
(3.3 V)
V
REF
BG GND/GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2SEL1
BIAS V
CC
V
CC
(5 V)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.