Datasheet

SN74GTLPH16916
17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES347B – JANUARY 2001 – REVISED AUGUST 2001
3–237
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
1 of 17 Channels
CE
CE
CLKOUT
CLKIN
1
56
55
2
28
30
29
27
3
54
31
26
V
REF
35