Datasheet
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
3–221
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of Texas Instruments’ Widebus
Family
D UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, and Clock-Enabled Modes
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTLP Outputs (50 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLPH16912 is a medium-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes
of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and
a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down
to 19 Ω.
GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP
(V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
Copyright 2001, Texas Instruments Incorporated
OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DGG OR DGV PACKAGE
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OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
BIAS V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA