Datasheet

SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
3–215
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
†
INPUTS
OUTPUT
CEAB OEAB LEAB CLKAB A
B
MODE
X H X X X Z Isolation
L L L H X B
0
‡
L LL LXB
0
§
Latched storage of A data
X L H X L L
X LH X H H
True transparent
L L L ↑ L L
L LL ↑ HH
Clocked storage of A data
H L L X X B
0
§
Clock inhibit
†
A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA
, OEBA, LEBA, and
CLKBA. The condition when OEAB
and OEBA are both low at the same time is not
recommended.
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low.
§
Output level before the indicated steady-state input conditions were established.
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
To 17 Other Channels
CE
CE
1
56
55
2
28
30
29
27
3
54
V
REF
35