Datasheet
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C – MARCH 2000 – REVISED AUGUST 2001
3–214
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
V
CC
(5 V) supplies the internal and GTLP circuitry, while V
CC
(3.3 V) supplies the LVTTL output buffers.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube SN74GTLPH16612DL
–40°C to 85°C
SSOP – DL
Tape and reel SN74GTLPH16612DLR
GTLPH16612
TSSOP – DGG Tape and reel SN74GTLPH16612GR GTLPH16612
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLPH16612 is a medium-drive (34 mA), 18-bit UBT transceiver, containing D-type latches and
D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes can replace any
of the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16612 UBT Transceiver Replacement Functions
FUNCTION 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT
Transceiver ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863
Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825
Latched transceiver ’543 ’16543 ’16472
Latch ’373, ’573 ’843 ’841 ’16373 ’16843
Registered transceiver ’646, ’652 ’16646, ’16652 ’16474
Flip-flop ’374, ’574 ’821 ’16374
Standard UBT ’16500, ’16501
Universal bus driver ’16835
Registered transceiver with clock enable ’2952 ’16470, ’16952
Flip-flop with clock enable ’377 ’823 ’16823
Standard UBT with clock enable ’16600, ’16601
SN74GTLPH16612 UBT transceiver replaces all above functions
Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and
LEBA), clock (CLKAB and CLKBA), and output enables (OEAB
and OEBA).
For A-to-B data flow, when CEAB
is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB
and LEAB are low, the A data
is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.
When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B-to-A is similar to that of A-to-B, except that CEBA
, OEBA, LEBA, and CLKBA are used.