Datasheet

SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326C MARCH 2000 REVISED AUGUST 2001
3–213
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Member of Texas Instruments Widebus
Family
D UBTTransceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, or Clock-Enabled Mode
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D LVTTL Interfaces are 5-V Tolerant
D Medium-Drive GTLP Outputs (34 mA)
D LVTTL Outputs (32 mA/64 mA)
D GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
Supports Partial-Power-Down Mode
Operation
D Bus Hold on A-Port Inputs
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description
The SN74GTLPH16612 is a medium-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of
data transfer. This device provides a high-speed interface between cards operating at LVTTL logic levels and
backplanes operating at GTLP signal levels. High-speed (about two times faster than standard LVTTL or TTL)
backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
OEC circuitry. These improvements minimize bus-settling time and have been designed and tested using
several backplane models.
GTLP is a TI derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac
specification of the SN74GTLPH16612 is given only at the preferred higher noise-margin GTLP, but the user
has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and
V
REF
= 1 V) signal levels.
The B port normally operates at GTLP levels, while the A-port and control inputs are compatible with LVTTL
logic levels and are 5-V tolerant. V
REF
is the reference input voltage for the B port.
To improve signal integrity, the SN74GTLPH16612 B-port output transition time is optimized for distributed
backplane loads.
Copyright 2001, Texas Instruments Incorporated
OEC, TI, UBT, and Widebus are trademarks of Texas Instruments.
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OEAB
LEAB
A1
GND
A2
A3
V
CC
(3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
(3.3 V)
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
V
CC
(5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
DGG OR DL PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.