Datasheet

SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
3–188
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN NOM MAX UNIT
V
CC
,
BIAS V
CC
Supply voltage 3.15 3.3 3.45 V
GTL 1.14 1.2 1.26
V
TT
Termination voltage
GTLP
1.35 1.5 1.65
V
GTL 0.74 0.8 0.87
V
REF
Reference voltage
GTLP
0.87 1 1.1
V
B port V
TT
V
I
Input voltage
Except B port and V
REF
V
CC
5.5
V
B port V
REF
+0.05
V
IH
High-level input voltage
Except B port
2
V
B port V
REF
–0.05
V
IL
Low-level input voltage
Except B port
0.8
V
I
IK
Input clamp current –18 mA
I
OH
High-level output current AO –24 mA
AO 24
I
OL
Low-level output current
B port 100
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆V
CC
Power-up ramp rate 20 µs/V
T
A
Operating free-air temperature –40 85 °C
NOTES: 4. All unused control and B-port inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
CC
= 3.3 V first, I/O second, and V
CC
= 3.3
V last, because the BIAS V
CC
precharge circuitry is disabled when any V
CC
pin is connected. The control and V
REF
inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable but, generally, GND is connected first.
6. V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.
7. V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when V
TT
> 0.7 V above V
REF
. If operated in the A-to-B direction, V
REF
should be set to within 0.6 V of V
TT
to
minimize current drain.