Datasheet

SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
3–179
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
†
TYP
‡
UNIT
t
PLH
AI
4.7
t
PHL
(buffer)
B Slow
5
ns
t
PLH
AI
3.7
t
PHL
(buffer)
B Fast
4
ns
t
PLH
LEAB
5.5
t
PHL
(latch mode)
B Slow
5.8
ns
t
PLH
LEAB
4.6
t
PHL
(latch mode)
B Fast
4.8
ns
t
PLH
CLKAB
5.8
t
PHL
(flip-flop mode)
B Slow
6
ns
t
PLH
CLKAB
4.9
t
PHL
(flip-flop mode)
B Fast
4.9
ns
t
PLH
5.5
t
PHL
OMODE
B Slow
5.7
ns
t
PLH
4.5
t
PHL
OMODE
B Fast
4.7
ns
Slow 1.8
t
r
Rise time, B-port outputs (20% to 80%)
Fast 1.1
ns
Slow 3.4
t
f
Fall time, B-port outputs (80% to 20%)
Fast 2.6
ns
†
Slow (ERC = H) and Fast (ERC = L)
‡
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.