Datasheet

SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
3–175
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
†
MIN TYP
‡
MAX UNIT
f
max
175 MHz
t
PLH
AI
3 7.4
t
PHL
(buffer)
B Slow
3 7.1
ns
t
PLH
AI
2 5.9
t
PHL
(buffer)
B Fast
2 5.8
ns
t
PLH
B
1 6.1
t
PHL
B
(buffer)
AO –
1 5.4
ns
t
PLH
LEAB
4.2 8.6
t
PHL
(latch mode)
B Slow
3.2 7.7
ns
t
PLH
LEAB
3.2 7.6
t
PHL
(latch mode)
B Fast
2.8 6.7
ns
t
PLH
LEAB
2 7.3
t
PHL
(latch mode)
AO –
1.8 6.6
ns
t
PLH
LEBA
1 6
t
PHL
LEBA
(latch mode)
AO –
1 5.2
ns
t
PLH
3.8 7.5
t
PHL
OEAB
B Slow
3.1 7
ns
t
PLH
2.5 6
t
PHL
OEAB
B Fast
2.5 6
ns
t
PLH
3.5 7.5
t
PHL
OEAB B Slow
3 7.2
ns
t
PLH
2.5 6
t
PHL
OEAB B Fast
2.5 6
ns
t
PZH
1 5.3
t
PZL
OEBA AO –
1 4.2
ns
t
PHZ
1 5.5
t
PLZ
OEBA AO –
1 5.2
ns
t
PLH
CLKAB
4.4 8.8
t
PHL
(flip-flop mode)
B Slow
3.6 8.1
ns
t
PLH
CLKAB
3.2 7.2
t
PHL
(flip-flop mode)
B Fast
3.1 6.9
ns
t
PLH
CLKAB
2 7.5
t
PHL
(flip-flop mode)
AO –
1.8 7
ns
t
PLH
CLKBA
1 6
t
PHL
(flip-flop mode)
AO –
1 5.6
ns
t
PLH
3.8 8.7
t
PHL
OMODE
B Slow
3.2 8.2
ns
t
PLH
2.7 7.2
t
PHL
OMODE
B Fast
2.7 7.2
ns
t
PLH
1 6
t
PHL
IMODE AO –
1 5.1
ns
†
Slow (ERC = H) and Fast (ERC = L)
‡
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.