Datasheet

SN74GTLP22033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES354C – JUNE 2001 – REVISED SEPTEMBER 2001
3–169
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
LOOPBACK
LOOPBACK
Q
†
L B port
H Point P
‡
†
Q is the input to the B-to-A
logic element.
‡
P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
SELECTED
MODE1 MODE0
LOGIC ELEMENT
L L Buffer
L H Flip-flop
H X Latch
FLIP-FLOP
INPUTS
CLK/LE DATA
OUTPUT
L X Q
0
↑ LH
↑ H L
B-PORT EDGE-RATE CONTROL (ERC)
INPUT
ERC
OUTPUT
B-PORT
LOGIC LEVEL
EDGE RATE
H Slow
L Fast