Datasheet

SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
3–158
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (unless otherwise noted)
MIN MAX UNIT
f
clock
Clock frequency 175 MHz
t
w
Pulse duration CLKAB/LEAB or CLKBA/LEBA 2.8 ns
AI before CLKAB 1.1
AI before CLKBA 1.4
B before CLKBA 1
t
su
Setup time
AI before LEAB
1.6
ns
AI before LEBA 2.1
B before LEBA 2.2
AI after CLKAB 0.3
AI after CLKBA 0.2
B after CLKBA 0.6
t
h
Hold time
AI after LEAB 0.3
ns
AI after LEBA 0
B after LEBA 0