Datasheet

SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001
3–154
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
CLKBA/LEBA
OEAB
OEAB
OMODE0
OMODE1
CLKAB/LEAB
AI1
IMODE0
IMODE1
B1
AO1
OEBA
LOOPBACK
44
41
24
25
38
2
48
1
35
3
32
29
46
One of Eight Channels
Transceiver
1D
C1
1D
C1
1D
C1
1D
C1
P
Q
V
REF
ERC
26
42
Pin numbers shown are for the DGG and DGV packages.