Datasheet

SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001
3–152
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
FUNCTION/MODE
INPUTS
OEBA OEAB OEAB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK
OUTPUT MODE
L L X X X X X X
L XH X X X X X
Z Isolation
X H L L L X X X Buffer
X HL L H X X X
Inverted AI to B
Flip-flop
X HL H X X X X Latch
H L X X X L L L
H XH X X L L L
Inverted B to AO
Buffer
H L X X X L H L
H XH X X L H L
Inverted B to AO
Flip-flop
H L X X X H X L
H XH X X H X L
Inverted B to AO
Latch
H L X X X L L H
H XH X X L L H
AI to AO Buffer
H L X X X L H H
H XH X X L H H
AI to AO
Flip-flop
H L X X X H X H
H XH X X H X H
AI to AO Latch
H H L X X X X L
Inverted AI to B,
Inverted B to AO
Transparent with
feedback path
ENABLE/DISABLE
INPUTS
OUTPUTS
OEBA OEAB OEAB AO B
L X X Z
H X X Active
X LL Z
X LH Z
X HL Active
X H H Z
BUFFER
INPUT
OUTPUT
L H
H L
LATCH
INPUTS
CLK/LE DATA
OUTPUT
H L H
H HL
L X Q
0