Datasheet

SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C – OCTOBER 1999 – REVISED AUGUST 2001
3–138
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
OUTPUT ENABLE
INPUTS
OUTPUTS
OE OEAB OEBA A PORT B PORT
L L L Active Active
†
L LH ZActive
L H L Active Z
L HH Z Z
H X X Z Z
†
This condition is not recommended.
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC
OUTPUT
LOGIC
LEVEL
NOMINAL
VOLTAGE
B-PORT
EDGE RATE
H V
CC
Slow
L GND Fast
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
1B1
1OEAB
CLK
1LEAB
1LEBA
1OEBA
1A1
1
64
63
62
2
4
59
To Seven Other Channels
OE
33
ERC
61
V
REF
41