Datasheet
SN74GTLPH3245
32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES291C – OCTOBER 1999 – REVISED AUGUST 2001
3–126
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
†
1DIR
1OE
1A1
1B1
1V
REF
2DIR
2OE
2A1
2B1
To Seven Other Channels
1ERC
†
1V
CC
and 1BIAS V
CC
are associated with these channels.
To Seven Other Channels
B3
E1
A3
K3
F2
B4
A4
E6
K4
F5
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