Datasheet

SN74GTLPH3245
32-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES291C – OCTOBER 1999 REVISED AUGUST 2001
3–123
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Member of Texas Instruments Widebus+
Family
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D LVTTL Interfaces Are 5-V Tolerant
D High-Drive GTLP Outputs (100 mA)
D LVTTL Outputs (24 mA/24 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
description
The SN74GTLPH3245 is a high-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLPs reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11 .
GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH3245 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP
(V
TT
= 1.5 V and V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC
). Changing the ERC
input voltage between GND and V
CC
adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry is provided to hold unused or undriven LVTTL data inputs at a valid logic state. Use
of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
PRODUCT PREVIEW
Copyright 2001, Texas Instruments Incorporated
OEC, TI, TI-OPC, and Widebus+ are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.