Datasheet

SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
3–116
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1DIR
1OE
1A1
1B1
1
2
56
55
V
REF
42
2DIR
2OE
2A1
2B1
To Seven Other Channels
28
16
29
41
ERC
15
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.