Datasheet

SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D – OCTOBER 1999 – REVISED SEPTEMBER 2001
3–114
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC
). Changing the ERC
input voltage between GND and V
CC
adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE
) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
terminal assignments
123456
A 1A2
1A1 1DIR 1OE 1B1 1B2
B 1A4 1A3 GND GND 1B3 1B4
C 1A5 GND V
CC
V
CC
GND 1B5
D 1A7 1A6 GND GND 1B6 1B7
E GND 1A8 1B8 BIAS V
CC
F ERC 2A1 2B1 V
REF
G 2A2 2A3 GND GND 2B3 2B2
H 2A4 GND V
CC
V
CC
GND 2B4
J 2A5 2A6 GND GND 2B6 2B5
K 2A7 2A8 2DIR 2OE 2B8 2B7
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74GTLPH1645DGGR GTLPH1645
–40°C to 85°C
TVSOP – DGV Tape and reel SN74GTLPH1645DGVR GL45
VFBGA – GQL Tape and reel SN74GTLPH1645GQLR GL45
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
123456