Datasheet

SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–112
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
†
FSTA TYP
‡
UNIT
t
PLH
t
PHL
Slow –
t
PLH
A B ns
t
PHL
Fast –
t
PLH
t
PHL
Slow –
t
PLH
SYSCLK B ns
t
PHL
Fast –
t
PLH
t
PHL
Slow
t
PLH
GND
t
PHL
Fast
t
PLH
SYSCLK SSCLK ns
t
PHL
Slow
t
PLH
V
CC
t
PHL
Fast
Rise time, B and SSCLK outputs
Slow – 1.6
t
r
(20% to 80%)
Fast – 1
ns
Fall time, B and SSCLK outputs
Slow – 1.5
t
f
(80% to 20%)
Fast – 1.6
ns
†
Slow (ERC = H) and Fast (ERC = L)
‡
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
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