Datasheet

SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–110
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYSCLK
B1
A
B18
SSCLK
SYSCLK to B t
PLH
SYSCLK to B t
PHL
∆B ∆B
SYSCLK to SSCLK
FSTA (Fast)
SYSCLK to SSCLK
FSTA (Slow)
SYSCLK to SSCLK
FSTA (Fast)
SYSCLK to SSCLK
FSTA (Slow)
t
sk(LH)
FSTA (Fast)
t
sk(LH)
FSTA (Slow)
t
sk(HL)
FSTA (Fast)
t
sk(HL)
FSTA (Slow)
1.5 V
Test
Point
C
L
= 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2 ns, t
f
≤ 2 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. Load circuit for B outputs is also used for SSCLK.
Figure 2. Load Circuit and SYSCLK to SSCLK + ∆B Skew Waveforms
PRODUCT PREVIEW