Datasheet

SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–108
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
REF
= 1 V (unless otherwise noted); standard lumped loads, C
L
= 30 pF for B port
(see Figure 1) (continued)
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE
RATE
‡
FSTA
TEST
CONDITIONS
MIN TYP
§
MAX UNIT
Slow –
t
sk(t)
¶
SYSCLK
B
Fast –
ns
t
sk(prLH)
#
t
sk(prHL)
#
SYSCLK
B Slow –
ns
t
sk(prLH)
#
t
sk(prHL)
#
SYSCLK
B Fast –
ns
†
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
‡
Slow (ERC = H) and Fast (ERC = L)
§
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
¶
t
sk(LH)
/t
sk(HL)
and t
sk(t)
– Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case V
CC
and temperature. The specifications apply to
any outputs switching in the same direction, either high to low [t
sk(HL)
], low to high [t
sk(LH)
] or in opposite directions, both low to high and high
to low [t
sk(t)
].
#
t
sk(prLH)
or t
sk(prHL)
– Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs
from device to device. The parameter is specified for a specific worst-case V
CC
and temperature. Furthermore, these values are provided by
SPICE simulations.
PRODUCT PREVIEW