Datasheet

EXPLANATION OF FUNCTION TABLES
1–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Among the most complex function tables are those of the shift registers. These embody most of the symbols used
in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register.
FUNCTION TABLE
INPUTS
OUTPUTS
CLEAR
MODE
CLOCK
SERIAL PARALLEL
Q
A
Q
B
Q
C
Q
D
CLEAR
S1 S0
CLOCK
LEFT RIGHT A B C D
Q
A
Q
B
Q
C
Q
D
L X X X X X X X X X L L L L
H X XL X XXXXXQ
A0
Q
B0
Q
C0
Q
D0
H H H ↑ X Xabcd a bcd
H L H ↑ X HHHHH HQ
An
Q
Bn
Q
Cn
H L H ↑ X LLLLL LQ
An
Q
Bn
Q
Cn
H H L ↑ H XXXXXQ
Bn
Q
Cn
Q
Dn
H
H H L ↑ L XXXXXQ
Bn
Q
Cn
Q
Dn
L
H L L X X X X X X X Q
A0
Q
B0
Q
C0
Q
D0
The first line of the table represents a synchronous clearing of the register and says that if clear is low, all four outputs
will be reset low regardless of the other inputs. In the following lines, clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low (while clear is high), no other input has any effect
and the outputs maintain the levels they assumed before the steady-state combination of clear high and clock low
was established. Since on other lines of the table only the rising transition of the clock is shown to be active, the second
line implicitly shows that no further change in the outputs occurs while the clock remains high or on the high-to-low
transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if S1 and S0 are both
high then, without regard to the serial input, the data entered at A is at output Q
A
, data entered at B is at Q
B
, and so
forth, following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data, respectively, from the shift-right serial input
and the shifting of previously entered data one bit; data previously at Q
A
is now at Q
B
, the previous levels of Q
B
and
Q
C
are now at Q
C
and Q
D
, respectively, and the data previously at Q
D
is no longer in the register. This entry of serial
data and shift takes place on the low-to-high transition of the clock when S1 is low and S0 is high and the levels at
inputs A through D have no effect.
The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial
input and the shifting of previously entered data one bit; data previously at Q
B
is now at Q
A
, the previous levels of
Q
C
and Q
D
are now at Q
B
and Q
C
, respectively, and the data previously at Q
A
is no longer in the register. This entry
of serial data and shift takes place on the low-to-high transition of the clock when S1 is high and S0 is low and the
levels at inputs A through D have no effect.
The last line shows that as long as both inputs are low, no other input has any effect and, as in the second line, the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs
low was established.
The function table functional tests do not reflect all possible combinations or sequential modes.