Datasheet

SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–101
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
A-TO-B DIRECTION
INPUTS
OUTPUTS
CKOE OE CMS DIR SYSCLK A SSCLK CLKOUT B
MODE
L L X L H or L X SYSCLK SYSCLK B
0
Latched storage of A
L L X L ↑ L SYSCLK SYSCLK L
Source
L LXL ↑ H SYSCLK SYSCLK H
Clocked storage of A
synchronous
L H X L X X SYSCLK SYSCLK Z Data isolation
H L X L X L Z Z L
H LXL X H Z ZH
Transparent transmission of A
H H X X X X Z Z Z Isolation
L H H X ↑ X SYSCLK SYSCLK Z
L H H X H or L X SYSCLK SYSCLK Z
Transmit SYSCLK
B-TO-A DIRECTION
INPUTS
OUTPUTS
CKOE OE CMS DIR SYSCLK SSCLK B SSCLK CLKOUT A
MODE
L L L H X H or L X Input SSCLK A
0
Latched storage of B
L L L H X ↑ L Input SSCLK L
Source
L LLH X ↑ H Input SSCLK H
Clocked storage of B
synchronous
L H L H X X X Input SSCLK Z Data isolation
L L H H H or L Output X SYSCLK SYSCLK A
0
Latched storage of B
L L H H ↑ Output L SYSCLK SYSCLK L
Clock
L LHH ↑ Output H SYSCLK SYSCLK H
Clocked storage of B
synchronous
L H H H X Output X SYSCLK SYSCLK Z Data isolation
H L X H X Output L Z Z L
H L X H X Output H Z ZH
Transparent transmission of B
H H X X X Output X Z Z Z Isolation
L H L X X ↑ X Input SSCLK Z
L H L X X H or L X Input SSCLK Z
Receive SSCLK
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC
OUTPUT
B-PORT
LOGIC LEVEL
EDGE RATE
H Slow
L Fast
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