Datasheet

SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–100
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
FSTA
OE
DIR
CMS
CKOE
A1 1D
C1
CLK
1D
C1
CLK
SYSCLK
CLKOUT
B1
V
REF
SSCLK
2
1
10
32
3
31
64
33
34
55
62
To Seventeen Other Channels
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