Datasheet
SN74GTLPH1627
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE SYNCHRONOUS CLOCK OUTPUTS
SCES356B – JUNE 2001 – REVISED SEPTEMBER 2001
3–97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D GTLP Buffered SYSCLK Signal (SSCLK) for
Source Synchronous Applications
D LVTTL Interfaces Are 5-V Tolerant
D High-Drive GTLP Outputs (100 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
description
The SN74GTLPH1627 is a high-drive, 18-bit bus
transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The
device allows for transparent and latched modes
of data transfer. Additionally, with the use of the
clock-mode select (CMS) input, the device can be
used in source synchronous and clock
synchronous applications. Source synchronous
applications require the skew between the clock
output and data output to be minimized for
optimum maximum-frequency system performance. In order to reduce this skew, aflexible setup time
adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock
and data. The CMS and direction (DIR) inputs control the mode of the device. The system clock (SYSCLK) and
CLKOUT pins are LVTTL compatible, while the source synchronous I/O is GTLP compatible. The benefits
include compensation for output-to-output skew coming from the driver itself, and compensation for process
skew if more than one driver is used. The device provides a high-speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than
standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced
input threshold levels, improved differential input, OECcircuitry, and TI-OPC circuitry. Improved GTLP OEC
and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane
models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load
impedance down to 11 Ω.
PRODUCT PREVIEW
Copyright 2001, Texas Instruments Incorporated
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
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DIR
OE
A1
A2
GND
A3
V
CC
A4
A5
CMS
A6
GND
A7
A8
A9
V
CC
A10
GND
A11
A12
GND
A13
A14
GND
A15
V
CC
A16
GND
A17
A18
CLKOUT
CKOE
FSTA
BIAS V
CC
B1
B2
GND
B3
ERC
B4
B5
V
REF
B6
GND
B7
B8
B9
V
CC
B10
GND
B11
B12
GND
B13
B14
GND
B15
V
CC
B16
GND
B17
B18
SSCLK
SYSCLK
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.