Datasheet

SN74GTLPH1616
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES346C– JANUARY 2001 – REVISED AUGUST 2001
3–87
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
1 of 17 Channels
CE
CE
CLKOUT
CLKIN
1
64
63
2
32
34
33
31
3
62
35
30
ERC
28
V
REF
39