Datasheet

SN74GTLPH1616
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES346C– JANUARY 2001 – REVISED AUGUST 2001
3–86
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
OUTPUT ENABLE
†
INPUTS
OUTPUT
CEAB OEAB LEAB CLKAB A
B
MODE
X H X X X Z Isolation
L L L H X B
0
‡
L LL LXB
0
§
Latched storage of A data
X L H X L L
X LH X H H
True transparent
L L L ↑ L L
L LL ↑ HH
Clocked storage of A data
H L L X X B
0
§
Clock inhibit
†
A-to-B data flow is shown: B-to-A data flow is similar, but uses CEBA
, OEBA, LEBA, and
CLKBA. The condition when OEAB
and OEBA are both low at the same time is not
recommended.
‡
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
§
Output level before the indicated steady-state input conditions were established
BUFFERED CLOCK
INPUTS
OPERATION OR
CE LE OEAB OEBA
FUNCTION
MODE
X X H H Z Isolation
X X L H CLKAB to CLKOUT
X X H L CLKOUT to CLKIN
True delayed clock signal
X X L L
CLKAB to CLKOUT,
CLKOUT to CLKIN
True delayed clock signal
with feedback path
¶
¶
This condition is not recommended.
B-PORT EDGE-RATE CONTROL (ERC
)
INPUT ERC
OUTPUT
LOGIC
LEVEL
NOMINAL
VOLTAGE
B-PORT
EDGE RATE
L GND Slow
H V
CC
Fast