Datasheet
SN74GTLPH1616
17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCES346C– JANUARY 2001 – REVISED AUGUST 2001
3–83
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of Texas Instruments’ Widebus
Family
D UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, or Clock-Enabled Modes
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D GTLP Buffered CLKAB Signal (CLKOUT)
D LVTTL Interfaces Are 5-V Tolerant
D High-Drive GTLP Outputs (100 mA)
D LVTTL Outputs (–24 mA/24 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
The SN74GTLPH1616 is a high-drive, 17-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of
data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion of
a GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 11 Ω.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.
DGG PACKAGE
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OEAB
LEAB
A1
A2
GND
A3
V
CC
A4
A5
GND
A6
A7
A8
GND
A9
V
CC
A10
GND
A11
A12
GND
A13
A14
GND
A15
V
CC
A16
ERC
A17
CLKIN
OEBA
LEBA
CEAB
CLKAB
B1
B2
GND
B3
BIAS V
CC
B4
B5
GND
B6
B7
B8
GND
B9
V
CC
B10
GND
B11
B12
GND
B13
B14
GND
B15
V
REF
B16
GND
B17
CLKOUT
CLKBA
CEBA